Program Continuation:

System cycle time/scan time divider corrected for digital drive

The machine data 10050 SYSCLOCK_CYCLE_TIME (system clock cycle time) and/or MD 10080 SYSCLOCK_SAMPL_TIME_RATIO (dividing factor of the position control cycle for actual value acquisition) have been corrected. If this requirement cannot be satisfied with the entered values (e.g. because the system clock cycle time is not a multiple of 31.25 ms), then the system clock cycle time is automatically expanded until the drive clock cycle time lies within the 31.25 ms grid.

The modifications were so made that, due to the selection of the system clock cycle time in MD 10050 SYSCLOCK_CYCLE_TIME, the programmable hardware divider 1 was readjusted in such a way that the selected time and the basic drive cycle result in a 31.25 ms grid. If this requirement is unfeasible (e.g. because the system clock cycle is not a multiple of 31.25 ms), the system clock cycle is automatically increased until the basic drive cycle is in a 31.25 ms grid.

The new value of the SYSCLOCK_CYCLE_TIME can be obtained from the MD 10050.

The position control cycle can be set with the following gradations:

up to 4 ms: 125 ps step

up to 8 ms: 250 ps step

up to 16 ms: 0.5 ms step

up to 32 ms: 1 ms step

- Alarm display.

No remedial measures are required. The alarm display can be canceled with Reset. Clear alarm with the Delete key or NC START.


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